The present invention relates generally to a method of designing semiconductor devices and more specifically to a method of designing semiconductor devices requiring planarization during fabrication.
Shallow Trench Isolation (STI) is a very attractive isolation technology for high-density complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits (ICs) on IC chips. The manufacture of IC chips using STI comprises laying out the desired devices of the circuit on a substrate having wells in the substrate, thus creating xe2x80x9cactive areas,xe2x80x9d and then using photomasking and etching processes to etch away trenches of constant depth and varying width between the active areas. Trench widths may vary greatly in relation to the spacing between active devices.
The trenches are then typically filled with a dielectric isolation material such as silicon oxide (SiO2) by a Chemical Vapor Deposition (CVD) process. The dielectric also builds on the active areas, however, so Chemical-Mechanical Polishing (CMP) processes are then used to planarize the chip. Planarization leaves a uniformly flat chip surface with each active area (AA) exposed and surrounded by isolation material. Planarization of dielectric-filled STI trenches of widely varying pattern density is quite difficult, however, because wide trenches may introduce non-uniformities in the CMP step, resulting in depressions or xe2x80x9cdishingxe2x80x9d in the subsequently planarized surface. To avoid such depressions and thus achieve global or long-range planarization, an additional planarization mask is often used to deposit material in the larger trenches. Local planarization is then achieved by the use of CMP.
In the next layer of the chip, photomasking and CVD processes are used to deposit Gate Conductor (GC) devices. Dielectric isolation material is deposited to fill the spaces between the GC devices, and the chip is again planarized by CMP processes. Often, widely varying GC pattern density will present the same type of gate planarization problems as experienced in planarization of the dielectric isolation between active areas.
To combat gate planarization problems, non-functional GC dummy shapes that are not part of a functional circuit may be added as fill between GC devices. These GC dummy shapes must be biased at ground to avoid formation of floating nodes that can present reliability problems. Such problems include, for example, an increased risk of process-induced damage.
Although the generation of GC dummy shapes is easily automated, the biasing of these shapes to ground is more difficult to automate. For example, a metal shape at ground may not exist near the GC dummy shape, or the connection path may be blocked by other metal shapes. Moreover, selection of a metal shape at ground requires voltage information in addition to simple geometric information about the layout. For these reasons, the biasing of the GC dummy shapes is often done manually. This task it tedious when included in the original design flow; it is even more difficult when applied to a completed design that did not anticipate the use of GC dummy shapes.
To achieve global planarization of the trench isolation without the need for and cost of a planarization mask, AA dummy shapes in addition to the functional AA shapes may be added in the large trenches, similar to the GC dummy shapes. Existing schemes for implementing these AA dummy shapes have drawbacks. For example, these AA dummy shapes may create floating parasitic diodes if their implanted source and drain are not biased at the same voltage as the underlying well. To prevent this drawback, the source-drain implant mask data can be designed so that the dummy AA shapes are always either substrate or well contacts. But this design requires a significant and cumbersome modification of the implant mask data. Furthermore, the AA dummy shapes may interfere with the GC dummy shapes.
Therefore, it is an object of the present invention to provide an integrated isolation and gate planarization method that provides coordinated AA fill and GC fill, that avoids the creation of floating nodes or diodes, and that provides a high density of AA and GC dummy shapes without requiring use of an additional planarization mask. It is also an object of the present invention to provide a GC fill biasing scheme which can be easily and completely automated and which can be applied to a completed design that did not anticipate the use of GC fill. It is a further feature of the GC biasing scheme that it may be used independent of the presence of AA fill.
To achieve these and other objects, and in view of its purposes, the present invention provides a planarization method for an integrated circuit chip comprising a substrate; a plurality of wells in the substrate, each well having a boundary; a functional active area shape located in one of the wells; and a functional gate conductor shape located in a layer above the functional active area shape. The planarization method comprises preventing dishing during gate planarization by creating a dummy gate conductor shape located neither over the well boundary nor over the functional active area shape. Floating nodes are prevented by electrically biasing the dummy gate conductor shape at a predetermined voltage. The predetermined voltage may be the voltage of the well underlying the dummy gate conductor shape. Biasing may be accomplished by providing an electrically conductive path between the dummy gate conductor shape and a well contact in an active area shape in the underlying well.
The integrated circuit chip may further comprise a shallow isolation trench adjacent the functional active area shape. The planarization method may further comprise preventing dishing during planarization of the dielectric isolation between active areas by creating a dummy active area shape in the isolation trench in a location that is not beneath a future functional gate conductor shape in the gate layer and is not over the well boundary in the substrate. The planarization method may further comprise designing the dummy gate conductor shape to completely cover the dummy active area shape.
The well underlying the dummy gate conductor may further have a voltage, and the biasing step may include biasing the dummy gate conductor at the well voltage. The biasing step may alternatively comprise biasing the dummy gate conductor at a voltage different from the underlying well voltage to create a decoupling capacitor. The biasing step may further comprise placing a well contact in an active area shape and electrically connecting the dummy gate conductor shape to the well contact to form a contact cell.
Where the well under-the dummy gate conductor shape is an N-well, this connecting step includes creating a well contact of N+ material over the N-well and providing a conducting path between the dummy gate conductor shape and the well contact. Where the well under the dummy gate conductor shape is a P-well, this connecting step includes creating a well contact of P+ material over the P-well and providing a conducting path between the dummy gate conductor shape and the well contact.
The integrated circuit chip resulting from the planarization method of the subject invention comprises a substrate; a plurality of wells in the substrate, each well having a boundary; a functional active area shape in one of the wells; a functional gate conductor shape in a layer above the functional active area shape; a dummy gate conductor shape in a location that is neither over a well boundary nor over the functional active area shape; and an electrical connection between the dummy gate conductor shape and a well contact in an active area shape. The integrated circuit chip may further comprise a dummy active area shape that is completely covered by the dummy gate conductor shape.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.